Exploring the relationship between tychoparthenogenesis and inbreeding depression in the Desert Locust, Schistocerca gregaria

Tychoparthenogenesis, a form of asexual reproduction in which a small proportion of unfertilized eggs can hatch spontaneously, could be an intermediate evolutionary link in the transition from sexual to parthenogenetic reproduction. The lower fitness of tychoparthenogenetic offspring could be due to either developmental constraints or to inbreeding depression in more homozygous individuals. We tested the hypothesis that in populations where inbreeding depression has been purged, tychoparthenogenesis may be less costly. To assess this hypothesis, we compared the impact of inbreeding and parthenogenetic treatments on eight life-history traits (five measuring inbreeding depression and three measuring inbreeding avoidance) in four laboratory populations of the desert locust, Schistocerca gregaria, with contrasted demographic histories. Overall, we found no clear relationship between the population history (illustrated by the levels of genetic diversity or inbreeding) and inbreeding depression, or between inbreeding depression and parthenogenetic capacity. First, there was a general lack of inbreeding depression in every population, except in two populations for two traits. This pattern could not be explained by the purging of inbreeding load in the studied populations. Second, we observed large differences between populations in their capacity to reproduce through tychoparthenogenesis. Only the oldest laboratory population successfully produced parthenogenetic offspring. However, the level of inbreeding depression did not explain the differences in parthenogenetic success between all studied populations. Differences in development constraints may arise driven by random and selective processes between populations. (Résumé d'auteur

Simultaneous floating-point sine and cosine for VLIW integer processors

Accepted for publication in the proceedings of the 23rd IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2012).International audienceGraphics and signal processing applications often require that sines and cosines be evaluated at a same floating-point argument, and in such cases a very fast computation of the pair of values is desirable. This paper studies how 32-bit VLIW integer architectures can be exploited in order to perform this task accurately for IEEE single precision. We describe software implementations for sinf, cosf, and sincosf over [-pi/4,pi/4] that have a proven 1-ulp accuracy and whose latency on STMicroelectronics' ST231 VLIW integer processor is 19, 18, and 19 cycles, respectively. Such performances are obtained by introducing a novel algorithm for simultaneous sine and cosine that combines univariate and bivariate polynomial evaluation schemes

Approximations par réécriture pour deux problèmes indécidables

National audiencePour vérifier des propriétés de sûreté ou de (non-)atteignabilité par model-checking régulier, on se concentre sur une modélisation des configurations accessibles du système par des langages réguliers et des relations d'évolution par des systèmes de réécriture. Le problème d'atteignabilité est indécidable dans de nombreux formalismes, et l'approche générale consiste à étudier et/ou à combiner des cas particuliers. Nous nous intéressons à l'approche par approximation pour semi-décider ce problème de vérification. Dans ce papier, nous exploitons l'analyse d'atteignabilité pour deux problèmes indécidables pour les machines de Turing : vacuité d'un langage et appartenance d'un mot à un langage. Nous proposons une modélisation et montrons comment les approximations par réécriture permettent de semi-décider ces problèmes. Cette approche a été implantée et expérimentée

Apc mutation induces resistance of colonic cells to lipoperoxide-triggered apoptosis induced by faecal water from haem-fed rats

Recent epidemiological studies suggest that high meat intake is associated with promotion of colon cancer linked to haem-iron intake. We previously reported that dietary haem, in the form of either haemoglobin or meat, promotes precancerous lesions in the colon of rats given a low-calcium diet. The mechanism of promotion by haem is not known, but is associated with increased lipid peroxidation in faecal water and strong cytotoxic activity of faecal water on a cancerous mouse colonic epithelial cell line. To better understand the involvement of faecal water components of haem-fed rats in colon cancer promotion, we explored the effect of faecal water on normal (Apc +/+) or premalignant cells (Apc Min/+). Further, we tested if this effect was correlated to lipoperoxidation and 4-hydroxynonenal (HNE). We show here for the first time that heterozygote Apc mutation represents a strong selective advantage, via resistance to apoptosis induction (caspase 3 pathway), for colonic cells exposed to a haem-iron induced lipoperoxidation. The fact that HNE treatment of the cells provoked the same effects as the faecal water of rats fed the haem-rich diet suggests that this compound triggers apoptosis in those cells. We propose that this mechanism could be involved in the promotion of colon carcinogenesis by haem in vivo

Non-generic floating-point software support for embedded media processing

International audienceThis paper presents some work in progress on the design and implementation of efficient floating-point software support for embedded integer processors. We provide quantitative evidence of the benefits of supporting various non-generic (that is, specialized, fused, or simultaneous) operations in addition to the five basic arithmetic operations: for individual calls, speedups range from 1.12 to 4.86, while on DSP kernels and benchmarks, our approach allows us to be up to 1.34x faster

Alternative Schemes for High-Bandwidth Instruction Fetching

Future processors combining out-of-order execution with aggressive speculation techniques will need to fetch multiple non-consecutive instruction blocks in a single cycle to achieve high-performance. Several high-bandwidth instruction fetching schemes have been proposed in the past few years. The Two-Block Ahead (TBA) branch predictor predicts two non-consecutive instruction blocks per cycle while relying on a conventional instruction cache. The trace cache (TC) records traces of instructions and delivers multiple non-consecutive instruction blocks to the execution core. The aim of this paper is to investigate the pros and cons of both approaches. Maintaining consistency between memory and TC is not a straightforward issue. We propose a simple hardware scheme to maintain consistency at a reasonable performance loss (1 to 5%). We also introduce a new fill unit heuristic for TC, the mispredict hint, that leads to significantly better performance (up to 20 %). This is mainly due to better prediction accuracy results and TC miss ratios. TBA requires double-ported or bank-interleaved structures to supply two non-consecutive blocks in a single cycle. We show that a 4-way interleaving scheme is cost-effective since it impairs performance by only 3 to 5%. Finally, simulation results show that such an enhanced TC scheme delivers higher performance than TBA when caches are large, due to a lower branch misprediction penalty and a higher instruction bandwidth on mispredictions. When the hardware budget is smaller, TBA outperforms TC because of a higher TC miss ratio and branch misprediction rate

How to square floats accurately and efficiently on the ST231 integer processor

We consider the problem of computing IEEE floating-point squares by means of integer arithmetic. We show how the specific properties of squaring can be exploited in order to design and implement algorithms that have much lower latency than those for general multiplication, while still guaranteeing correct rounding. Our algorithm descriptions are parameterized by the floating-point format, aim at high instruction-level parallelism (ILP) exposure, and cover all rounding modes. We show further that their C implementation for the binary32 format yields efficient codes for targets like the ST231 VLIW integer processor from STMicroelectronics, with a latency at least 1.75x smaller than that of general multiplication in the same context